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Circuit designs for low-power and SEU-hardened systems

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/9359

Circuit designs for low-power and SEU-hardened systems

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Title: Circuit designs for low-power and SEU-hardened systems
Author: Devarapalli, Vallabh Srikanth
Advisor(s): Payman, Zarkesh-Ha
Committee Member(s): Suddarth, Steven C.
Pollard, L. Howard
Department: University of New Mexico. Dept. of Electrical and Computer Engineering
Subject(s): Low Power
SEU-Hardening
LC Subject(s): Low voltage integrated circuits--Design and construction.
Radiation hardening.
Degree Level: Masters
Abstract: The desire to have smaller and faster portable devices is one of the primary motivations for technology scaling. Though advancements in device physics are moving at a very good pace, they might not be aggressive enough for now-a-day technology scaling trends. As a result, the MOS devices used for present day integrated circuits are pushed to the limit in terms of performance, power consumption and robustness, which are the most critical criteria for almost all applications. Secondly, technology advancements have led to design of complex chips with increasing chip densities and higher operating speeds. The design of such high performance complex chips (microprocessors, digital signal processors, etc) has massively increased the power dissipation and, as a result, the operating temperatures of these integrated circuits. In addition, due to the aggressive technology scaling the heat withstanding capabilities of the circuits is reducing, thereby increasing the cost of packaging and heat sink units. This led to the increase in prominence for smarter and more robust low-power circuit and system designs. Apart from power consumption, another criterion affected by technology scaling is robustness of the design, particularly for critical applications (security, medical, finance, etc). Thus, the need for error free or error immune designs. Until recently, radiation effects were a major concern in space applications only. With technology scaling reaching nanometer level, terrestrial radiation has become a growing concern. As a result Single Event Upsets (SEUs) have become a major challenge to robust designs. Single event upset is a temporary change in the state of a device due to a particle strike (usually from the radiation belts or from cosmic rays) which may manifest as an error at the output. This thesis proposes a novel method for adaptive digital designs to efficiently work with the lowest possible power consumption. This new technique improves options in performance, robustness and power. The thesis also proposes a new dual data rate flipflop, which reduces the necessary clock speed by half, drastically reducing the power consumption. This new dual data rate flip-flop design culminates in a proposed unique radiation hardened dual data rate flip-flop, “Firebird”. Firebird offers a valuable addition to the future circuit designs, especially with the increasing importance of the Single Event Upsets (SEUs) and power dissipation with technology scaling.
Graduation Date: May 2009
URI: http://hdl.handle.net/1928/9359

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