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Single event upset hardened CMOS combinational logic and clock buffer design

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/7631

Single event upset hardened CMOS combinational logic and clock buffer design

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Title: Single event upset hardened CMOS combinational logic and clock buffer design
Author: Mallajosyula, Aahlad
Advisor(s): Zarkesh-Ha, Payman
Committee Member(s): Krishna, Sanjay
Graham, Edward Jr
Department: University of New Mexico. Dept. of Electrical and Computer Engineering
Subject(s): Single Event Upset
Soft Error
Single Event Transient
Hardened
Combinational Logic
Clock Buffer
Soft Error Rate
CMOS
LC Subject(s): Metal oxide semiconductors, Complementary
Degree Level: Masters
Abstract: A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wrong logic level causing failure. Soft errors or Single Event Upsets (SEU) caused by radiation strikes are one of the main failure modes in a VLSI circuit. Previous work predicts that soft error rate may dominate the failure rate in VLSI circuit compared to all other failure modes put together. The issue of single event upsets (SEU) need to be addressed such that the failure rate of the chips dues to SEU is in the acceptable range. Memory circuits are designed to be error free with the help of error correction codes. Technology scaling is driving up the SEU rate of combinational logic and it is predicted that the soft error rate (SER) of combinational logic may dominate the SER of unpro-tected memory by the year 2011. Hence a robust combinational logic methodology must be designed for SEU hardening. Recent studies have also shown that clock distribution network is becoming increasingly vulnerable to radiation strike due to reduced capaci-tance at the clock leaf node. A strike on clock leaf node may propagate to many flip-flops increasing the system SER considerably. In this thesis we propose a novel method to improve the SER of the circuit by filtering single event upsets in the combinational logic and clock distribution network. Our ap-proach results in minimal circuit overhead and also requires minimal effort by the de-signer to implement the proposed method. In this thesis we focus on preventing the propagation of SEU rather than eliminating the SEU on each sensitive gate.
Graduation Date: December 2008
URI: http://hdl.handle.net/1928/7631

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