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dc.contributor.authorBezerra, George
dc.date.accessioned2012-08-27T22:27:01Z
dc.date.available2012-08-27T22:27:01Z
dc.date.issued2012-08-27
dc.date.submittedJuly 2012
dc.identifier.urihttp://hdl.handle.net/1928/21020
dc.description.abstractComputer architecture design is in a new era where performance is increased by replicating processing cores on a chip rather than making CPUs larger and faster. This design strategy is motivated by the superior energy efficiency of the multi-core architecture compared to the traditional monolithic CPU. If the trend continues as expected, the number of cores on a chip is predicted to grow exponentially over time as the density of transistors on a die increases. A major challenge to the efficiency of multi-core chips is the energy used for communication among cores over a Network on Chip (NoC). As the number of cores increases, this energy also increases, imposing serious constraints on design and performance of both applications and architectures. Therefore, understanding the impact of different design choices on NoC power and energy consumption is crucial to the success of the multi- and many-core designs. This dissertation proposes methods for modeling and optimizing energy consumption in multi- and many-core chips, with special focus on the energy used for communication on the NoC. We present a number of tools and models to optimize energy consumption and model its scaling behavior as the number of cores increases. We use synthetic traffic patterns and full system simulations to test and validate our methods. Finally, we take a step back and look at the evolution of computer hardware in the last 40 years and, using a scaling theory from biology, present a predictive theory for power-performance scaling in microprocessor systems.en_US
dc.language.isoenen_US
dc.subjectmulti-coreen_US
dc.subjectmany-coreen_US
dc.subjectenergy consumptionen_US
dc.subjectcommunicaiton localityen_US
dc.subjectscalingen_US
dc.subject.lcshNetworks on a chip--Energy consumption--Computer simulation.
dc.subject.lcshNetworks on a chip--Computer simulation.
dc.subject.lcshMicroprocessors--Energy consumption--Mathematical models.
dc.titleEnergy consumption in networks on chip : efficiency and scalingen_US
dc.typeDissertationen_US
dc.description.degreeComputer Scienceen_US
dc.description.levelDoctoralen_US
dc.description.departmentUniversity of New Mexico. Dept. of Computer Scienceen_US
dc.description.advisorForrest, Stephanie
dc.description.committee-memberMoses, Melanie
dc.description.committee-memberArnold, Dorian
dc.description.committee-memberZarkesh-Ha, Payman


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