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dc.contributor.authorJohnson, Richard
dc.date.accessioned2012-08-27T21:03:39Z
dc.date.available2012-08-27T21:03:39Z
dc.date.issued2012-08-27
dc.date.submittedJuly 2012
dc.identifier.urihttp://hdl.handle.net/1928/20986
dc.description.abstractThree-dimensional (3D) stacking of integrated circuits (ICs) is an enabling technology in the advancement of the microelectronics industry. 3D stacking enables increased device density per volume and improved electrical performance through short vertical interconnect paths. Mechanical reliability of 3D IC packages is critical due to the widespread use of electronic devices. Misalignment induced shear deformation of the through-silicon vias (TSV) and solder micro-bumps are simulated through an applied shearing action. Thermal effects due to coefficient of thermal expansion (CTE) mismatch during processing are also studied to provide trends of stress and deformation fields. Reliability of the 3D chip stack, TSV and solder micro-bump are assessed by examining local stresses and the buildup of plastic strain through series of parametric twodimensional (2D) and 3D finite element method (FEM) simulations. A special case when the solder joint is transformed into an intermetallic compound is also examined. Misalignment induced shearing strongly influences stresses and deformation in and around the micro-bump. Thermal CTE mismatches influence stresses and deformation in the entire 3D chip stack and in the TSV far away from the joint. Shortcomings of the 2D plane strain model for examining CTE mismatch and measuring buildup of plastic strain in the joint are also discussed.en_US
dc.language.isoen_USen_US
dc.subject3D ICen_US
dc.subjectThermalen_US
dc.subjectTSVen_US
dc.subjectMicrobumpen_US
dc.subjectchipen_US
dc.subject.lcshMultichip modules (Microelectronics)
dc.subject.lcshInterconnects (Integrated circuit technology)
dc.subject.lcshSolder and soldering.
dc.subject.lcshDeformation (Mechanics)Plasticity.
dc.subject.lcshPlasticity.
dc.titleNumerical analysis of TSV/micro-bump deformation due to chip misalignment and thermal processing in 3D IC packagesen_US
dc.typeThesisen_US
dc.description.degreeMechanical Engineeringen_US
dc.description.levelMastersen_US
dc.description.departmentUniversity of New Mexico. Dept. of Mechanical Engineeringen_US
dc.description.advisorShen, Yu-Lin
dc.description.committee-memberLeseman, Zyad
dc.description.committee-memberVorobieff, Peter


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