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Carbon nanotubes as interconnect for next generation network on chip


Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/20781

Carbon nanotubes as interconnect for next generation network on chip

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Title: Carbon nanotubes as interconnect for next generation network on chip
Author: Ramalingam Rajasekaran, Manoj Kumar
Advisor(s): Zarkesh Ha, Payman
Committee Member(s): Krishna, Sanjay
Fleddermann, Charles
Suddharth, Steven
Department: University of New Mexico. Dept. of Electrical and Computer Engineering
Subject: Carbon Nanotubes, Network on Chip, Interconnects
LC Subject(s): Interconnects (Integrated circuit technology)
Networks on a chip.
Degree Level: Masters
Abstract: Multi-core processors provide better performance when compared with their single-core equivalent. Recently, Networks-on-Chip (NoC) have emerged as a communication methodology for multi core chips. Network-on-Chip uses packet based communication for establishing a communication path between multiple cores connected via interconnects. Clock frequency, energy consumption and chip size are largely determined by these interconnects. According to the International Technology Roadmap for Semiconductors (ITRS), in the next five years up to 80% of microprocessor power will be consumed by interconnects. In the sub 100nm scaling range, interconnect behavior limits the performance and correctness of VLSI systems. The performance of copper interconnects tend to get reduced in the sub 100nm range and hence we need to examine other interconnect options. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current carrying capacity and large electron mean free paths. This work suggests using Single Wall Carbon Nanotubes (SWCNT) as interconnects for Networks-on-Chip as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires.
Graduation Date: May 2012
URI: http://hdl.handle.net/1928/20781

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