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Selective epitaxial growth techniques to integrate high-quality germanium on silicon

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/12863

Selective epitaxial growth techniques to integrate high-quality germanium on silicon

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Title: Selective epitaxial growth techniques to integrate high-quality germanium on silicon
Author: Leonhardt, Darin
Advisor(s): Han, Sang
Committee Member(s): Dawson, L. Ralph
Krishna, Sanjay
Datye, Abhaya
Department: University of New Mexico. Dept. of Chemical and Nuclear Engineering
Subject(s): Heteroepitaxy; Germanium; Silicon; Selective Growth; Electronic Materials
LC Subject(s): Molecular beam epitaxy.
Germanium crystals--Growth.
Degree Level: Doctoral
Abstract: High-quality Ge-on-Si heterostructures have been actively pursued for many advanced applications, including near-infrared photodetectors, high-mobility field effect transistors, and virtual substrates for integrating III-V multijunction solar cells. However, growing epitaxial Ge on Si poses many engineering challenges, ranging from lattice mismatch, to thermal expansion coefficient mismatch, to non-planar morphological evolution. The lattice mismatch between Ge and Si often leads to a high density of threading dislocations. These dislocations, if not reduced, propagate through the subsequently grown GaAs layer, deteriorating its quality. To overcome these engineering challenges, we have developed three different approaches based on molecular beam epitaxy to significantly reduce, manage, or eliminate the defects in Ge films grown on Si. The first approach involves the nucleation of Ge islands within nanoscale windows in a thin layer of chemically grown SiO2 and successive island coalescence over the SiO2 to form a continuous film. Nanoscale contact areas between Ge and Si effectively relieve the lattice mismatch stress between Ge/Si so that dislocations do not nucleate. We observe that annealing the nucleated islands prior to full coalescence also leads to Ge films that are free of defects, along with significant improvement in GaAs integrated on Ge. The second approach involves trapping dislocations in Ge between high aspect ratio walls of SiO2. Defects form during coalescence of Ge from adjacent channels and at the corners of the SiO2 walls due to stress resulting from differences in thermal expansion coefficients of Ge, Si, and SiO2. The third approach involves filling etch pits, which reveal dislocations, with SiO2 and subsequent Ge growth over SiO2. The filling prevents dislocations in the lower Ge layer from propagating into the upper Ge layer. The third method reduces the defect density from 2.8 ´ 108 cm-2 to 9.1 ´ 106 cm-2, and is proven to be the most effective at reducing the defects in epitaxial growth of Ge on Si. We expect that our engineering approaches may finally resolve a longstanding engineering challenge in heteroepitaxy, finally providing the cost reduction needed for widespread commercialization of multijunction solar cells, light-emitting diodes, and high-mobility transistors on Si substrates.
Graduation Date: May 2011
URI: http://hdl.handle.net/1928/12863

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