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dc.contributor.authorAarestad, James
dc.date.accessioned2011-07-02T15:27:44Z
dc.date.available2011-07-02T15:27:44Z
dc.date.issued2011-07-02
dc.date.submittedMay 2011
dc.identifier.urihttp://hdl.handle.net/1928/12832
dc.description.abstractVariations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this research work, a method is proposed for a flush delay technique to measure both regional delay variations and SOI history effect. The method is then validated using a test structure fabricated in a 65 nm SOI process.en_US
dc.description.sponsorshipNational Science Foundationen_US
dc.language.isoen_USen_US
dc.subjectDelay variationen_US
dc.subjectRegional Delay Variationen_US
dc.subjectSOI History Effecten_US
dc.subjectProcess Variationen_US
dc.subject.lcshDelay faults (Semiconductors)
dc.subject.lcshSilicon-on-insulator technology.
dc.titleCharacterizing within-die and die-to-die delay variations introduced By process variations and SOI history effecten_US
dc.typeThesisen_US
dc.description.degreeComputer Engineeringen_US
dc.description.levelMastersen_US
dc.description.departmentUniversity of New Mexico. Dept. of Electrical and Computer Engineeringen_US
dc.description.advisorPlusquellic, Jim
dc.description.committee-memberPlusquellic, Jim
dc.description.committee-memberZarkesh-Ha, Payman
dc.description.committee-memberPattichis, Marios


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