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A Physical Unclonable Function derived from the power distribution system of an integrated circuit


Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/12078

A Physical Unclonable Function derived from the power distribution system of an integrated circuit

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Title: A Physical Unclonable Function derived from the power distribution system of an integrated circuit
Author: Helinski, Ryan Lee
Advisor(s): Plusquellic, Jim
Committee Member(s): Zarkesh-Ha, Payman
Crandall, Jed
Acharyya, Dhruva
Department: University of New Mexico. Dept. of Electrical and Computer Engineering
Subject: process variations
physical unclonable function
hardware security
LC Subject(s): Computers--Circuits--Design and construction.
Integrated circuits--Verification.
Computer security.
Integrated passive components.
Public key cryptography.
Degree Level: Doctoral
Abstract: Hardware support for security mechanisms such as authentication, cryptographic protocols, digital rights management and hardware metering depend heavily on the security of embedded secret keys. The current practice of embedding these keys as digital data in the Integrated Circuit (IC) weakens security because the keys can be learned through attacks. Physical Unclonable Functions (PUFs) are a recently- proposed alternative to storing digital keys on the IC. A PUF leverages the inherent manufacturing variations of an IC to define a random function. However, poor performance under PUF quality criteria such as the level of randomness and reproducibility in the responses have detracted from their adoption and widespread use. In this dissertation, I propose several ways to define a novel PUF using the Power Distribution System (PDS) of an IC. First, I describe the hardware primitive and test setup that is required to obtain the PUF responses. Then, I evaluate the analog PUF responses from silicon against standard PUF quality metrics in order to qualify the strengths and weaknesses of the proposed PUF. I show that the analog PUFs ex- hibit very high levels of randomness and reproducibility, but are sensitive to changes in temperature. Next, I propose extensions to our PUF that enable an exponential number of Challenge/Response Pairs (CRPs) with respect to the number of hardware resources, as well as yielding a marginal increase in the level of randomness. I also use these same analog measurements from silicon to simulate an integrated implementation of the PUF that takes a digital challenge and returns a digital response. I show that the integrated architecture also exhibits high levels of randomness and reproducibility, and is also resistant to changes in temperature. Future work includes designing and building a new IC that implements a more powerful hardware primitive that will improve both the number and accuracy of the measurements, as well as additional hardware that will allow the challenge and response generation to be performed on-chip.
Graduation Date: December 2010
URI: http://hdl.handle.net/1928/12078

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