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FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/12052

FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY

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Title: FUNDAMENTAL ISSUE IN SPACE ELECTRONICS RELIABILITY: NEGATIVE BIAS TEMPERATURE INSTABILITY
Author: Mee, Jesse
Advisor(s): Lester, Luke
Committee Member(s): Lavrova, Olga
Devine, Roderick
Department: University of New Mexico. Dept. of Electrical and Computer Engineering
Subject(s): NBTI
Negative Bias Temperature Instability
Charge Trapping
Degree Level: Masters
Abstract: Negative Bias Temperature Instability (NBTI) in silicon based metal-oxide-semiconductor-field-effect-transistors (MOSFETs) has been recognized as a critical reliability issue for advanced space qualified electronics. The phenomenon manifests itself as a modification of threshold voltage (Vth) resulting in degraded signal timing paths, and ultimately circuit failure. Despite the obvious importance of the issue, a standard measurement protocol has yet to be determined. This is a consequence of a large amount of complexity introduced by the strong dependencies of NBTI on temperature, electric field, frequency, duty cycle, and gate dielectric composition. We have improved upon the traditional measurement techniques which suffered from an underestimation of the magnitude of Vth shifts because they failed to account for trapped charge relaxation. Specifically, we have developed a means for measuring the maximum effect of NBTI by virtue of a method that can continuously monitor the Vth(t) without having to remove the stressing voltage. The interpretation methodology for this technique is explained in detail and the relevant approximations are justified. We have evidenced temperature and vertical electric field dependent Vth shifts in SiO2 and HfSiON devices. Furthermore, we have collected substantial evidence that the traditional Vth=At analysis fails to explain the experimental data in the early time domain. Finally, we have discovered that Vth(t) on p-channel field effect transistors with HfSiON gate dielectrics is dependent upon the magnitude of Vds during the stressing cycle. To our knowledge this is not anticipated by any prior modeling attempts. We justify the exclusion of short channel effects as a possibility, leading us to conclude that positive charge in the dielectric stack is laterally
Graduation Date: December 2010
URI: http://hdl.handle.net/1928/12052

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