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SIMD pipelined processor implemented on a FPGA


Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/3278

SIMD pipelined processor implemented on a FPGA

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Title: SIMD pipelined processor implemented on a FPGA
Author: Mar, Benjamin
Advisor(s): Pattichis, Marios
Committee Member(s): Shu, Wei Wennie
Christodoulou, Christos
Department: University of New Mexico. Dept. of Electrical and Computer Engineering
Subject: SIMD
Signal processing--Digital techniques
LC Subject(s): Multiprocessors.
Parallel processing (Electronic computers)
Pipelining (Electronics)
VHDL (Computer hardware description language)
Field programmable gate arrays.
Degree Level: Masters
Abstract: The goal of this thesis was to create a processor using VHDL that could be used for educational purposes as well as a stepping stone in creating a reconfigurable system for digital signal processing or image processing applications. To do this a subset of MIPS instructions were chosen to demonstrate functionality within a five stage pipeline (instruction fetch, instruction decode, execution, memory, and write back) processor in simulation and in synthesis. A hazard controller was implemented to handle data forwarding and stalling. The basic MIPS architecture was extended by adding singlecycle multiplication functionality and single-cycle SIMD instructions. The architecture contains parameters for easy modification of SIMD units depending on the needs of the processor. The SIMD architecture was designed with distributed memory so that every memory unit received the same address. This simplifies the address logic so that the processor does not have to use a complex addressing mode. The memory can be pictured as row and columns method of access. The SIMD instructions were chosen to be able to perform binary operations to implement future morphological operations and to use the multiply and add operations for implementing MACs to perform convolution and filtering operations in future image processing applications. The board being used to verify the processor was a Xilinx University Program (XUP) board that contains Xilinx Virtex II Pro XC2VP30 FPGA, package FF896. The maximum number of units that can be instantiated in the FPGA on the XUP board is eight units which would use the entire FPGA slice area. This allows the processor to complete eight sets of 32-bit data operations per cycle when the SIMD pipeline is full. The design was shown to operate at the maximum speed of 100 MHz and utilize all the area of the FPGA. The processor was verified in both simulation and synthesis. The new soft-core 32-bit SIMD processor extends existing soft-core processors in that it provides a reconfigurable SIMD-pipeline allowing it to operate on multiple inputs concurrently, with 32-bit operands and a single-cycle throughput.
Graduation Date: July 2007
URI: http://hdl.handle.net/1928/3278

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