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Analog multiply and accumulate FPA readout circuit with digital multiply and sign maintenance

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/17438

Analog multiply and accumulate FPA readout circuit with digital multiply and sign maintenance

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Title: Analog multiply and accumulate FPA readout circuit with digital multiply and sign maintenance
Author: LeBoeuf, Thomas
Advisor(s): Zarkesh-Ha, Payman
Committee Member(s): Plusquellic, James
Graham, Edward
Department: University of New Mexico. Dept. of Electrical and Computer Engineering
Subject(s): analog circuits
analog signal processing
read out integrated circuit
ROIC
LC Subject(s): Signal processing ǂx Equipment and supplies.
Image processing ǂx Equipment and supplies.
Linear integrated circuits.
Degree Level: Masters
Abstract: The high bandwidth and power needed to process the data coming from modern high resolution focal plane arrays leads to the necessity for fast and efficient read out and data processing. A system that performs block recognition and image classification with efficiency and low latency is presented. The system is comprised of an analog signal processor that will be integrated into the read out integrated circuit. This enables the capability to read out the focal plane array information and process it completely in the analog domain in a comparably very small amount of operational steps. The steps and techniques of the design flow, including definition of problem, concepts and design of system architecture, simulation of system, and analog lay out practices are covered.
Graduation Date: December 2011
URI: http://hdl.handle.net/1928/17438

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