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Packaging Strategy for High Voltage and High Shock Environments

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/12925

Packaging Strategy for High Voltage and High Shock Environments

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Title: Packaging Strategy for High Voltage and High Shock Environments
Author: Austin, Kevin
Subject(s): High Viltage, Coating, Packaging
Abstract: The historical design approach for ensuring survivability in devices that operate at high voltages which would arc in air or that must survive substantial shock loadings employs an encapsulant whose dielectric strength prevents electrical breakdown and whose modulus prevents gross movement of the embedded components. While mostly successful, this approach presents some significant design challenges: (1) the high thermal expansion of the epoxy leads to large stresses during thermal cycles, (2) degassing of the epoxy before cure and careful encapsulation are essential to eliminate voids that could initiate dielectric breakdown, (3) the internal components are embedded deep within an impenetrable encapsulant and “removable” options have proven somewhat problematic, (4) the filled epoxy encapsulant adds weight. It is the intent of this study to develop a new design strategy that will eliminate these issues resulting in a cost effective, lighter and more robust component with fewer defects. The new paradigm rests on employing two materials, instead of just one, to achieve the desired effect. First, a thin coating applied to the board will provide both dielectric breakdown protection and/or support for components on boards. Second, a foam encapsulation will provide both bulk rigidity and damping in shock environments. This two-stage approach lessens dielectric requirements of the bulk encapsulant and shifts them to the coating. It also affords greater flexibility in optimizing materials and processing properties to achieve design objectives and enhanced manufacturability. Commercially available coatings have been chosen for the study to span a wide variety of application techniques and performance requirements. A standardized test, ASTM D149, was conducted on each coating to quantitatively compare dielectric coating strength at both room temp and a severe aging environment. For certain coatings it is proven that the dielectric strength degrades in a humid environment. These coatings were also placed on printed circuit board geometries with and without components and tested extensively using both DC and pulsed AC testing systems developed specifically for this study. In the absence of a coating, i.e., a bare board in an ambient air atmosphere, breakdown occurs at 10kV or less. For one of the geometries explored in this study, the results have shown that thin coatings of less than 5 mils (.127 mm) prevent breakdown up to or exceeding the 80kV or higher for flat wire traces. If, in addition to the thin coating, a bead coating is applied to high voltage electrical components with topographical contours, the breakdown voltage is in the 40-60 kV range for component gaps of 0.05 to 0.425 in. The use of a polyurethane foam encapsulant results in breakdown voltages of 50-70 kV for the same component gaps as long as the gap between components is not small enough to prevent the foam from filling it. Combining a foam and coating as the packaging can increase the breakdown voltage range to 50-80 kV for these component gaps. The adhesion strength of the polymer coatings was also characterized in its original state and after aging in a humid environment. In many cases, adhesion strength is known to degrade in humid environments. The adhesion strength of the coatings to the printed circuit board interface is considerably lower than that found for epoxy bonds using epoxy adhesives of equivalent glass transition temperatures. Foam adhesion to the coatings was also characterized. Adhesion between the packaging foam and coatings was found to be either maximized at 249 psi or minimized at 48 psi depending on the coating chosen. Contact angle measurements were made to study wetting ability. Equilibrium contact angles for all coatings on solder mask are reached in less than 3 minutes. The results of this study demonstrate the viability of this novel packaging strategy.
Date: 2011-08-01
Series: ;SAND Number 2011-1830 P
URI: http://hdl.handle.net/1928/12925

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