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Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect

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Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/12832

Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect

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Title: Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect
Author: Aarestad, James
Advisor(s): Plusquellic, Jim
Committee Member(s): Plusquellic, Jim
Zarkesh-Ha, Payman
Pattichis, Marios
Department: University of New Mexico. Dept. of Electrical and Computer Engineering
Subject: Delay variation
Regional Delay Variation
SOI History Effect
Process Variation
LC Subject(s): Delay faults (Semiconductors)
Silicon-on-insulator technology.
Degree Level: Masters
Abstract: Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this research work, a method is proposed for a flush delay technique to measure both regional delay variations and SOI history effect. The method is then validated using a test structure fabricated in a 65 nm SOI process.
Graduation Date: May 2011
URI: http://hdl.handle.net/1928/12832


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