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Using ant colony optimization for routing in microprocesors


Please use this identifier to cite or link to this item: http://hdl.handle.net/1928/10258

Using ant colony optimization for routing in microprocesors

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Title: Using ant colony optimization for routing in microprocesors
Author: Arora, Tamanna
Advisor(s): Moses, Melanie
Committee Member(s): Luger, George F.
Zarkesh-Ha, Payman
Department: University of New Mexico. Dept. of Computer Science
Subject(s): VLSI
LC Subject(s): Integrated circuits--Very large scale integration--Computer-aided design.
Microprocessors--Computer-aided design.
Ant algorithms.
Degree Level: Masters
Abstract: Power consumption is an important constraint on VLSI systems. With the advancement in technology, it is now possible to pack a large range of functionalities into VLSI devices. Hence it is important to find out ways to utilize these functionalities with optimized power consumption. This work focuses on curbing power consumption at the design stage. This work emphasizes minimizing active power consumption by minimizing the load capacitance of the chip. Capacitance of wires and vias can be minimized using Ant Colony Optimization (ACO) algorithms. ACO provides a multi agent framework for combinatorial optimization problems and hence is used to handle multiple constraints of minimizing wire-length and vias to achieve the goal of minimizing capacitance and hence power consumption. The ACO developed here is able to achieve an 8% reduction of wire-length and 7% reduction in vias thereby providing a 7% reduction in total capacitance, compared to other state of the art routers.
Graduation Date: December 2009
URI: http://hdl.handle.net/1928/10258

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